1. Field of the Invention
The present invention relates in general to a memory interface control circuit. In particular, the present invention relates to a memory interface control circuit to combine and support a plurality of memories of different types in a memory control chip.
2. Description of the Related Art
Recently, the operating rates of central processing units (CPU) and bandwidth of computer systems are increasing, so the bandwidth of peripherals have to be increased to improve operating efficiency. The peripherals include memory, display card, and hard disks. While early memory uses dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM) is being substituted for DRAM because the rate of DRAM is slow. Although standards of SDRAM have improved from PC-66, PC-100, and PC-133 through PC-150, speed of SDRAM still presents a bottleneck.
The newest memory is double date rate DRAM (DDR-DRAM). DDR-DRAM accesses double data during a clock operation, and the total accessed data rate is doubled to improve operating efficiency. However, DDR-DRAM is too expensive to substitute for SDRAM at this time. Thus, the computer system usually comprises SDRAM and DDR-DRAM slots simultaneously, and comprises a memory control chip to control both SDRAM and DDR-DRAM. Moreover, the cost is decreased when the SDRAM and DDR-DRAM are merged in the memory control chip.
However, since pin counts, power, and interface of SDRAM and DDR-DRAM are different, it is hard to merge SDRAM and DDR-DRAM with a memory control chip and on a main board. FIG. 2 shows the connection of the conventional SDRAM. FIG. 3 shows the connection of the conventional DDR-DRAM. The SDRAM and DDR-DRAM are all connected to the memory control chip 50. The pin number of the dual inline memory module (DIMM) 30 of SDRAM is 168, and the pin number of the dual inline memory module (DIMM) 40 of DDR-DRAM is 184. The voltage supplied to the SDRAM DIMM 30 is 3.3V, high-level signal is 2.0V, and low-level signal is 0.8V. In addition, the voltage supplied to the DDR-DRAM DIMM 40 is 2.5V, high-level signal is VTT+0.35V, and low-level signal is VTTxe2x88x920.35V. Here, VTT is 1.25V. The resistors 41 are coupled between VTT and DDR-DRAM DIMM 40. Since there are many standard differences between SDRAM DIMM 30 and DDR-DRAM DIMM 40, it is very difficult to merge SDRAM DIMM 30 and DDR-DRAM DIMM 40 in a main board.
The object of the present invention is to provide a memory interface circuit to control memories of different types by adding peripheral circuitry.
Another object of the present invention is to provide a memory interface control circuit that includes a power switching circuit and a terminal switch. When the SDRAM is inserted into the SDRAM DIMM, the voltage level of a predetermined pin of SDRAM DIMM will be changed. Then, the power switching circuit and the terminal switch respond by switching to adjust the voltage supplied to the memory and the peripheral circuits. Thus, the memory control chip can drive memories of different types.